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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file contains video PHY functionality specific to the HDMI protocol. </p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
           dd/mm/yy
</p>
<hr/>
<p>
1.0   gm   10/12/18 Initial release.
1.1   ku   24/07/20 Program MMCM params based on max line rate
                    configured in IP GUI
1.2   ssh  02/02/23 Added API for Clock Detector Accuracy Range
1.3   ssh  17/07/23 Added support for MMCM/PLL Clock Primitive
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#a70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 *Id0, u8 *Id1)</td></tr>
<tr class="memdesc:a70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.  <a href="#a70ecb3c5614ea8c97c0bc56bd395ac2c">More...</a><br/></td></tr>
<tr class="separator:a70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa15dd35a9b1670aab091738d3ecca9df"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a> *CfgPtr)</td></tr>
<tr class="memdesc:gaa15dd35a9b1670aab091738d3ecca9df"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the Video PHY for HDMI.  <a href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">More...</a><br/></td></tr>
<tr class="separator:gaa15dd35a9b1670aab091738d3ecca9df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d8702f582054727e5bafc4e6cf32739"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> TxSysPllClkSel, <a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> RxSysPllClkSel)</td></tr>
<tr class="memdesc:ga1d8702f582054727e5bafc4e6cf32739"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Updates the HDMIPHY clocking.  <a href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">More...</a><br/></td></tr>
<tr class="separator:ga1d8702f582054727e5bafc4e6cf32739"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a355efb9fbbf8e3d0102738e912971bca"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#a355efb9fbbf8e3d0102738e912971bca">XHdmiphy1_TxAlignReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Reset)</td></tr>
<tr class="memdesc:a355efb9fbbf8e3d0102738e912971bca"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the GT TX alignment module.  <a href="#a355efb9fbbf8e3d0102738e912971bca">More...</a><br/></td></tr>
<tr class="separator:a355efb9fbbf8e3d0102738e912971bca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a579cfbb41fbd51477dd902f9a1758826"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#a579cfbb41fbd51477dd902f9a1758826">XHdmiphy1_TxAlignStart</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Start)</td></tr>
<tr class="memdesc:a579cfbb41fbd51477dd902f9a1758826"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the GT TX alignment module.  <a href="#a579cfbb41fbd51477dd902f9a1758826">More...</a><br/></td></tr>
<tr class="separator:a579cfbb41fbd51477dd902f9a1758826"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2369998b0e4635bced93881e51cc8fe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab2369998b0e4635bced93881e51cc8fe">XHdmiphy1_ClkDetEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gab2369998b0e4635bced93881e51cc8fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the HDMIPHY's detector peripheral.  <a href="group__xhdmiphy1.html#gab2369998b0e4635bced93881e51cc8fe">More...</a><br/></td></tr>
<tr class="separator:gab2369998b0e4635bced93881e51cc8fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2f877b2581399c3344d1555d05df2df"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac2f877b2581399c3344d1555d05df2df">XHdmiphy1_ClkDetTimerClear</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gac2f877b2581399c3344d1555d05df2df"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the clock detector TX/RX timer.  <a href="group__xhdmiphy1.html#gac2f877b2581399c3344d1555d05df2df">More...</a><br/></td></tr>
<tr class="separator:gac2f877b2581399c3344d1555d05df2df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac39e0926826a1e127514c8350ddcde21"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac39e0926826a1e127514c8350ddcde21">XHdmiphy1_ClkDetFreqReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gac39e0926826a1e127514c8350ddcde21"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets clock detector TX/RX frequency.  <a href="group__xhdmiphy1.html#gac39e0926826a1e127514c8350ddcde21">More...</a><br/></td></tr>
<tr class="separator:gac39e0926826a1e127514c8350ddcde21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5a055146c6b3aa1da1991a0041dc11f7">XHdmiphy1_ClkDetSetFreqLockThreshold</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u16 ThresholdVal)</td></tr>
<tr class="memdesc:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the clock detector frequency lock counter threshold value.  <a href="group__xhdmiphy1.html#ga5a055146c6b3aa1da1991a0041dc11f7">More...</a><br/></td></tr>
<tr class="separator:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa113dd9ce96c346ef9b757947eb340fe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa113dd9ce96c346ef9b757947eb340fe">XHdmiphy1_ClkDetAccuracyRange</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u16 ThresholdVal)</td></tr>
<tr class="memdesc:gaa113dd9ce96c346ef9b757947eb340fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the clock detector accuracy range value.  <a href="group__xhdmiphy1.html#gaa113dd9ce96c346ef9b757947eb340fe">More...</a><br/></td></tr>
<tr class="separator:gaa113dd9ce96c346ef9b757947eb340fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafaece55136a95db26cf37edcd53c96f8"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafaece55136a95db26cf37edcd53c96f8">XHdmiphy1_ClkDetCheckFreqZero</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gafaece55136a95db26cf37edcd53c96f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks clock detector RX/TX frequency zero indicator bit.  <a href="group__xhdmiphy1.html#gafaece55136a95db26cf37edcd53c96f8">More...</a><br/></td></tr>
<tr class="separator:gafaece55136a95db26cf37edcd53c96f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga46cb7e8a6cc10a61bbfb7126f85e8cec">XHdmiphy1_ClkDetSetFreqTimeout</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u32 TimeoutVal)</td></tr>
<tr class="memdesc:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets clock detector frequency lock counter threshold value.  <a href="group__xhdmiphy1.html#ga46cb7e8a6cc10a61bbfb7126f85e8cec">More...</a><br/></td></tr>
<tr class="separator:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbffa1bd1304f2f69a32aa1a22573052"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gacbffa1bd1304f2f69a32aa1a22573052">XHdmiphy1_ClkDetTimerLoad</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u32 TimeoutVal)</td></tr>
<tr class="memdesc:gacbffa1bd1304f2f69a32aa1a22573052"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function loads the timer to TX/RX in the clock detector.  <a href="group__xhdmiphy1.html#gacbffa1bd1304f2f69a32aa1a22573052">More...</a><br/></td></tr>
<tr class="separator:gacbffa1bd1304f2f69a32aa1a22573052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb75647ab6dfd99febccba18593e86d8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gabb75647ab6dfd99febccba18593e86d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral.  <a href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">More...</a><br/></td></tr>
<tr class="separator:gabb75647ab6dfd99febccba18593e86d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2d190888890d12b1524b5d5065e5e57"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gae2d190888890d12b1524b5d5065e5e57"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral.  <a href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">More...</a><br/></td></tr>
<tr class="separator:gae2d190888890d12b1524b5d5065e5e57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ccf265013fcb1e013775dc9a8563c87"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">XHdmiphy1_DruReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Reset)</td></tr>
<tr class="memdesc:ga5ccf265013fcb1e013775dc9a8563c87"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the DRU in the HDMIPHY.  <a href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">More...</a><br/></td></tr>
<tr class="separator:ga5ccf265013fcb1e013775dc9a8563c87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b7a69d580eaac17960b977851aead25"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">XHdmiphy1_DruEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Enable)</td></tr>
<tr class="memdesc:ga7b7a69d580eaac17960b977851aead25"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enabled/disables the DRU in the HDMIPHY.  <a href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">More...</a><br/></td></tr>
<tr class="separator:ga7b7a69d580eaac17960b977851aead25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5da59924fa5189f7141d950e6d31a50"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab5da59924fa5189f7141d950e6d31a50">XHdmiphy1_DruGetVersion</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gab5da59924fa5189f7141d950e6d31a50"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the DRU version.  <a href="group__xhdmiphy1.html#gab5da59924fa5189f7141d950e6d31a50">More...</a><br/></td></tr>
<tr class="separator:gab5da59924fa5189f7141d950e6d31a50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02899710d93b44ffa5d6f87637d67809"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">XHdmiphy1_DruSetCenterFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u64 CenterFreqHz)</td></tr>
<tr class="memdesc:ga02899710d93b44ffa5d6f87637d67809"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the DRU center frequency.  <a href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">More...</a><br/></td></tr>
<tr class="separator:ga02899710d93b44ffa5d6f87637d67809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c7a948926fede8a6548c6cffe5fc830"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga4c7a948926fede8a6548c6cffe5fc830">XHdmiphy1_DruCalcCenterFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga4c7a948926fede8a6548c6cffe5fc830"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the center frequency value for the DRU.  <a href="group__xhdmiphy1.html#ga4c7a948926fede8a6548c6cffe5fc830">More...</a><br/></td></tr>
<tr class="separator:ga4c7a948926fede8a6548c6cffe5fc830"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">XHdmiphy1_HdmiGtDruModeEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the GT RX CDR and Equalization for DRU mode.  <a href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">More...</a><br/></td></tr>
<tr class="separator:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa361514e8315c25876867a1ded2c99b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc)</td></tr>
<tr class="memdesc:gafa361514e8315c25876867a1ded2c99b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the HDMI MMCM parameters.  <a href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">More...</a><br/></td></tr>
<tr class="separator:gafa361514e8315c25876867a1ded2c99b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a026bd874ba52e36d8f0e770b962543f9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:a026bd874ba52e36d8f0e770b962543f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the QPLL parameters.  <a href="#a026bd874ba52e36d8f0e770b962543f9">More...</a><br/></td></tr>
<tr class="separator:a026bd874ba52e36d8f0e770b962543f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefc037877ed6316c6995845442a31971"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#aefc037877ed6316c6995845442a31971">XHdmiphy1_HdmiCpllParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:aefc037877ed6316c6995845442a31971"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the CPLL parameters.  <a href="#aefc037877ed6316c6995845442a31971">More...</a><br/></td></tr>
<tr class="separator:aefc037877ed6316c6995845442a31971"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69e679f0c4444350910817be69cde77c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">XHdmiphy1_SetHdmiTxParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc, XVidC_ColorFormat ColorFormat)</td></tr>
<tr class="memdesc:ga69e679f0c4444350910817be69cde77c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function update/set the HDMI TX parameter.  <a href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">More...</a><br/></td></tr>
<tr class="separator:ga69e679f0c4444350910817be69cde77c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2bf27809a22eecc5194a8bad16261280"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">XHdmiphy1_SetHdmiRxParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga2bf27809a22eecc5194a8bad16261280"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function update/set the HDMI RX parameter.  <a href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">More...</a><br/></td></tr>
<tr class="separator:ga2bf27809a22eecc5194a8bad16261280"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafe6529e3429c7199f87f7f8fc7f43fe0">XHdmiphy1_PatgenEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, u8 Enable)</td></tr>
<tr class="memdesc:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock.  <a href="group__xhdmiphy1.html#gafe6529e3429c7199f87f7f8fc7f43fe0">More...</a><br/></td></tr>
<tr class="separator:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51d10d93fa76ebe0c031600b61955d4d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga51d10d93fa76ebe0c031600b61955d4d">XHdmiphy1_PatgenSetRatio</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, u64 TxLineRate)</td></tr>
<tr class="memdesc:ga51d10d93fa76ebe0c031600b61955d4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock.  <a href="group__xhdmiphy1.html#ga51d10d93fa76ebe0c031600b61955d4d">More...</a><br/></td></tr>
<tr class="separator:ga51d10d93fa76ebe0c031600b61955d4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">XHdmiphy1_Hdmi20Config</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the HDMIPHY to HDMI 2.0 mode.  <a href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">More...</a><br/></td></tr>
<tr class="separator:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6379077b417b3f435699335235439978"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xhdmiphy1__hdmi_8c.html#a6379077b417b3f435699335235439978">Xhdmiphy1_RefClkValue</a> ()</td></tr>
<tr class="memdesc:a6379077b417b3f435699335235439978"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the FRL REF CLK for HDMI 2.1 operation.  <a href="#a6379077b417b3f435699335235439978">More...</a><br/></td></tr>
<tr class="separator:a6379077b417b3f435699335235439978"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2aa401218d0bc4c64c2210f85ccee457"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels)</td></tr>
<tr class="memdesc:ga2aa401218d0bc4c64c2210f85ccee457"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the GT for HDMI 2.1 operation.  <a href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">More...</a><br/></td></tr>
<tr class="separator:ga2aa401218d0bc4c64c2210f85ccee457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints Video PHY debug information related to HDMI.  <a href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">More...</a><br/></td></tr>
<tr class="separator:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="a70ecb3c5614ea8c97c0bc56bd395ac2c"></a>
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          <td class="memname">void XHdmiphy1_Ch2Ids </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Id0</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Id1</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. </p>
<p>HDMI uses 3 channels; This ID translation is done to allow other functions to operate iteratively over multiple channels.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> core instance. </td></tr>
    <tr><td class="paramname">ChId</td><td>is the channel ID used to determine the indices. </td></tr>
    <tr><td class="paramname">Id0</td><td>is a pointer to the start channel ID to set. </td></tr>
    <tr><td class="paramname">Id1</td><td>is a pointer to the end channel ID to set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The contents of Id0 and Id1 will be set according to ChId. </dd></dl>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate()</a>, <a class="el" href="group__xhdmiphy1.html#gaf3cb368774462d22b085a8e34d2c7a00">XHdmiphy1_CfgPllRefClkSel()</a>, <a class="el" href="group__xhdmiphy1.html#ga4e6b72ef1579950b4c8c83e35e7ad4b0">XHdmiphy1_CfgSysClkDataSel()</a>, <a class="el" href="group__xhdmiphy1.html#ga738210e1c11e69176f1cd733ff0bae6c">XHdmiphy1_CfgSysClkOutSel()</a>, <a class="el" href="group__xhdmiphy1.html#gad8f3d6250fe7c2d7384a5f20507da509">XHdmiphy1_ClkCalcParams()</a>, <a class="el" href="group__xhdmiphy1.html#gaeb31d823a71bad5b0bb6250b016577d7">XHdmiphy1_ClkReconfig()</a>, <a class="el" href="group__xhdmiphy1.html#gacfaf4756f5682dfda2739a8083deea56">XHdmiphy1_DirReconfig()</a>, <a class="el" href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">XHdmiphy1_DruEnable()</a>, <a class="el" href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">XHdmiphy1_DruReset()</a>, <a class="el" href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">XHdmiphy1_DruSetCenterFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#acc32a98d0cf6cf638c3fe4e3fe057226">XHdmiphy1_HdmiCpllLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#aefc037877ed6316c6995845442a31971">XHdmiphy1_HdmiCpllParam()</a>, <a class="el" href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">XHdmiphy1_HdmiGtDruModeEnable()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a0c603299dc1bafabcf0ecfe920bd412b">XHdmiphy1_HdmiGtRxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#aa2c97194ee284139b2959025092cc122">XHdmiphy1_HdmiGtTxAlignDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a0dadbdee261d92500f5c3a5f55b76218">XHdmiphy1_HdmiQpllLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga5a0a82f90d7a0f1c4c8180cfb465de0a">XHdmiphy1_HdmiRxTimerTimeoutHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#gada0844e8a6a828bb7d512259aca11498">XHdmiphy1_HdmiTxTimerTimeoutHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection()</a>, <a class="el" href="group__xhdmiphy1.html#ga03e2d2bdcf56e256ff08f5776313a76e">XHdmiphy1_OutDivReconfig()</a>, <a class="el" href="group__xhdmiphy1.html#ga87f9523a81f1b648cfae0172bdd96f0b">XHdmiphy1_PllCalculator()</a>, <a class="el" href="group__xhdmiphy1.html#gaf1fbb7de9d26abab7332a62932be9d85">XHdmiphy1_PowerDownGtPll()</a>, <a class="el" href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">XHdmiphy1_SetPrbsSel()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a355efb9fbbf8e3d0102738e912971bca">XHdmiphy1_TxAlignReset()</a>, and <a class="el" href="xhdmiphy1__hdmi_8c.html#a579cfbb41fbd51477dd902f9a1758826">XHdmiphy1_TxAlignStart()</a>.</p>

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          <td class="memname">u32 XHdmiphy1_HdmiCpllParam </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>QuadId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XHdmiphy1_DirectionType&#160;</td>
          <td class="paramname"><em>Dir</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function calculates the CPLL parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the HDMI GT core instance. </td></tr>
    <tr><td class="paramname">QuadId</td><td>is the GT quad ID to operate on. </td></tr>
    <tr><td class="paramname">ChId</td><td>is the channel ID to operate on. </td></tr>
    <tr><td class="paramname">Dir</td><td>is an indicator for RX or TX.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if calculated CPLL parameters updated successfully.</li>
<li>XST_FAILURE if parameters not updated.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_hdmiphy1.html#ae19e95b6e84e21a988ba6910ceb3f35a">XHdmiphy1::Config</a>, <a class="el" href="struct_x_hdmiphy1___config.html#ac28bbc6cb3c52b7dfc77813be0af0be5">XHdmiphy1_Config::DruIsPresent</a>, <a class="el" href="struct_x_hdmiphy1.html#a247ba8ff835a604c754d34ab3ba0450c">XHdmiphy1::HdmiRxDruIsEnabled</a>, <a class="el" href="struct_x_hdmiphy1.html#a9ba8d9489de84bdfb6acc4d33c7957ea">XHdmiphy1::HdmiRxRefClkHz</a>, <a class="el" href="struct_x_hdmiphy1.html#a74efe69af6760d2c3cf8d4d471f5591d">XHdmiphy1::HdmiRxTmdsClockRatio</a>, <a class="el" href="struct_x_hdmiphy1.html#a834eecec514b7571575a3bf47cfa63e0">XHdmiphy1::HdmiTxRefClkHz</a>, <a class="el" href="struct_x_hdmiphy1.html#aa0e3e6f1c5e328af0628bc58d19e915a">XHdmiphy1::HdmiTxSampleRate</a>, <a class="el" href="struct_x_hdmiphy1___hdmi21_cfg.html#aa0dc355514f68382f6bfaced2f6e979b">XHdmiphy1_Hdmi21Cfg::IsEnabled</a>, <a class="el" href="struct_x_hdmiphy1___hdmi21_cfg.html#a724279f7463626815c9b4abf031a1bca">XHdmiphy1_Hdmi21Cfg::LineRate</a>, <a class="el" href="struct_x_hdmiphy1.html#a0204ec609474b091ff494d61ebd2aa80">XHdmiphy1::Quads</a>, <a class="el" href="struct_x_hdmiphy1.html#a44a9b24f205fee3e03f3724a89abf2bb">XHdmiphy1::RxHdmi21Cfg</a>, <a class="el" href="struct_x_hdmiphy1___config.html#ad065247f3924daf6806ef1cd334ba877">XHdmiphy1_Config::TransceiverWidth</a>, <a class="el" href="struct_x_hdmiphy1.html#ac60ed4c71a5adcb71a99edad2997e24c">XHdmiphy1::TxHdmi21Cfg</a>, <a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#gad8f3d6250fe7c2d7384a5f20507da509">XHdmiphy1_ClkCalcParams()</a>, <a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga3fc9cb2326efad44689d4af163343b7f">XHdmiphy1_ErrorHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">XHdmiphy1_GetLineRateHz()</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa16d87e8ac61927ee62d631af02a55eea">XHDMIPHY1_LOG_EVT_DRU_CLK_ERR</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa1591a806934dc21fa2368d022cd0f12d">XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad34e90440aa943deb81d65f994e7272b">XHDMIPHY1_LOG_EVT_NO_DRU</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fabf63790d5f5a16fdfbbd3c5d2680fa29">XHDMIPHY1_LOG_EVT_USRCLK_ERR</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa1c67cc48ccc5a88ac43e15fe694879b6">XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR</a>, and <a class="el" href="group__xhdmiphy1.html#gabda0c5df35f1e8c13b871c8edf38ff38">XHdmiphy1_LogWrite()</a>.</p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">XHdmiphy1_SetHdmiRxParam()</a>, and <a class="el" href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">XHdmiphy1_SetHdmiTxParam()</a>.</p>

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          <td class="memname">u32 XHdmiphy1_HdmiQpllParam </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>QuadId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XHdmiphy1_DirectionType&#160;</td>
          <td class="paramname"><em>Dir</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function calculates the QPLL parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the HDMI GT core instance. </td></tr>
    <tr><td class="paramname">QuadId</td><td>is the GT quad ID to operate on. </td></tr>
    <tr><td class="paramname">ChId</td><td>is the channel ID to operate on. </td></tr>
    <tr><td class="paramname">Dir</td><td>is an indicator for RX or TX.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if calculated QPLL parameters updated successfully.</li>
<li>XST_FAILURE if parameters not updated.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_hdmiphy1.html#ae19e95b6e84e21a988ba6910ceb3f35a">XHdmiphy1::Config</a>, <a class="el" href="struct_x_hdmiphy1___config.html#ac28bbc6cb3c52b7dfc77813be0af0be5">XHdmiphy1_Config::DruIsPresent</a>, <a class="el" href="struct_x_hdmiphy1.html#a247ba8ff835a604c754d34ab3ba0450c">XHdmiphy1::HdmiRxDruIsEnabled</a>, <a class="el" href="struct_x_hdmiphy1.html#a9ba8d9489de84bdfb6acc4d33c7957ea">XHdmiphy1::HdmiRxRefClkHz</a>, <a class="el" href="struct_x_hdmiphy1.html#a74efe69af6760d2c3cf8d4d471f5591d">XHdmiphy1::HdmiRxTmdsClockRatio</a>, <a class="el" href="struct_x_hdmiphy1.html#a834eecec514b7571575a3bf47cfa63e0">XHdmiphy1::HdmiTxRefClkHz</a>, <a class="el" href="struct_x_hdmiphy1.html#aa0e3e6f1c5e328af0628bc58d19e915a">XHdmiphy1::HdmiTxSampleRate</a>, <a class="el" href="struct_x_hdmiphy1___hdmi21_cfg.html#aa0dc355514f68382f6bfaced2f6e979b">XHdmiphy1_Hdmi21Cfg::IsEnabled</a>, <a class="el" href="struct_x_hdmiphy1___hdmi21_cfg.html#a724279f7463626815c9b4abf031a1bca">XHdmiphy1_Hdmi21Cfg::LineRate</a>, <a class="el" href="struct_x_hdmiphy1.html#a0204ec609474b091ff494d61ebd2aa80">XHdmiphy1::Quads</a>, <a class="el" href="struct_x_hdmiphy1___channel.html#ab051d1c6482506f1b3469f4f7310be01">XHdmiphy1_Channel::RxDataWidth</a>, <a class="el" href="struct_x_hdmiphy1.html#a44a9b24f205fee3e03f3724a89abf2bb">XHdmiphy1::RxHdmi21Cfg</a>, <a class="el" href="struct_x_hdmiphy1___channel.html#abdf0d23bac376e9bab185c7625cc74e3">XHdmiphy1_Channel::RxIntDataWidth</a>, <a class="el" href="struct_x_hdmiphy1___config.html#ad065247f3924daf6806ef1cd334ba877">XHdmiphy1_Config::TransceiverWidth</a>, <a class="el" href="struct_x_hdmiphy1.html#ac60ed4c71a5adcb71a99edad2997e24c">XHdmiphy1::TxHdmi21Cfg</a>, <a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate()</a>, <a class="el" href="group__xhdmiphy1.html#ga4e6b72ef1579950b4c8c83e35e7ad4b0">XHdmiphy1_CfgSysClkDataSel()</a>, <a class="el" href="group__xhdmiphy1.html#ga738210e1c11e69176f1cd733ff0bae6c">XHdmiphy1_CfgSysClkOutSel()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#gad8f3d6250fe7c2d7384a5f20507da509">XHdmiphy1_ClkCalcParams()</a>, <a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga3fc9cb2326efad44689d4af163343b7f">XHdmiphy1_ErrorHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">XHdmiphy1_GetLineRateHz()</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa16d87e8ac61927ee62d631af02a55eea">XHDMIPHY1_LOG_EVT_DRU_CLK_ERR</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fac16c7e8601244f595cd804fe75df142b">XHDMIPHY1_LOG_EVT_GT_QPLL_CFG_ERR</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad34e90440aa943deb81d65f994e7272b">XHDMIPHY1_LOG_EVT_NO_DRU</a>, <a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fabf63790d5f5a16fdfbbd3c5d2680fa29">XHDMIPHY1_LOG_EVT_USRCLK_ERR</a>, and <a class="el" href="group__xhdmiphy1.html#gabda0c5df35f1e8c13b871c8edf38ff38">XHdmiphy1_LogWrite()</a>.</p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">XHdmiphy1_SetHdmiRxParam()</a>, and <a class="el" href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">XHdmiphy1_SetHdmiTxParam()</a>.</p>

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          <td class="memname">u32 Xhdmiphy1_RefClkValue </td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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<p>This function will configure the FRL REF CLK for HDMI 2.1 operation. </p>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>FRL Ref Clk value</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, and <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>.</p>

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          <td class="memname">void XHdmiphy1_TxAlignReset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function resets the GT TX alignment module. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> core instance. </td></tr>
    <tr><td class="paramname">ChId</td><td>is the channel ID to operate on. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or deassert reset on the TX alignment module, respectively.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_hdmiphy1___config.html#a2bbcc590627355bad185ca417e839a6e">XHdmiphy1_Config::BaseAddr</a>, <a class="el" href="struct_x_hdmiphy1.html#ae19e95b6e84e21a988ba6910ceb3f35a">XHdmiphy1::Config</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#ga962d997981e2e284c3c9dd0e8a9a5752">XHdmiphy1_ReadReg</a>, and <a class="el" href="group__xhdmiphy1.html#ga9e65226a4b7cf835cf8555e84d895555">XHdmiphy1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>.</p>

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          <td class="memname">void XHdmiphy1_TxAlignStart </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Start</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function resets the GT TX alignment module. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> core instance. </td></tr>
    <tr><td class="paramname">ChId</td><td>is the channel ID to operate on. </td></tr>
    <tr><td class="paramname">Start</td><td>specifies TRUE/FALSE value to either start or ttop the TX alignment module, respectively.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_hdmiphy1___config.html#a2bbcc590627355bad185ca417e839a6e">XHdmiphy1_Config::BaseAddr</a>, <a class="el" href="struct_x_hdmiphy1.html#ae19e95b6e84e21a988ba6910ceb3f35a">XHdmiphy1::Config</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#ga962d997981e2e284c3c9dd0e8a9a5752">XHdmiphy1_ReadReg</a>, and <a class="el" href="group__xhdmiphy1.html#ga9e65226a4b7cf835cf8555e84d895555">XHdmiphy1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#gada0844e8a6a828bb7d512259aca11498">XHdmiphy1_HdmiTxTimerTimeoutHandler()</a>.</p>

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